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Monday, March 21, 2011

Binary Counter

Kuliah Minggu 11 (Part 1)

Desimal Counter
Mengira kosong hingga lima ratus lima puluh bukan suatu yang rumit. Ringkasnya, apa yang berlaku ialah :
Pada setiap pertukaran nombor, didapati, digit pertama akan sentiasa berubah/bertukar, dan digit kedua akan berubah setiap sepuluh kali digit yang pertama telah berubah. Dan digit ketiga berubah setiap sepuluh kali digit kedua telah berubah. Digit adalah (0 - 9).

Contoh : 000 hingga 550

000
001
002
003
004
.
.
.
009
010 //Digit kedua berubah kepada 1 setelah digit pertama berubah 10 kali.
011
012
.
.
.
.
.
099
100 //Digit ketiga berubah kepada 1 setelah digit kedua berubah 10 kali.
101
.
.
.
.
550




Binary Counter?
Ini yang nak dibincangkan dalam kuliah 11. Ada tiga perkara :
1. Asynchronous Binary Counter 2. Synchronous Binary Counter 3. Up/Down Synchronous Binary Counter


Counter : Synchronous versus Asynchronous
As applied to inputs:
A change on a synchronous input doesn’t affect the outputs until the next active clock edge, but a change on an asynchronous input affects the outputs immediately.
As applied to counters:
in a synchronous counter, the outputs can all change at the same instant; but in an asynchronous counter, there’s a brief delay between the changing of the outputs.


Some Asynchronous Counter ICs
  • 7490 Four bit decade counter (MOD 10)
  • 7492 Four bit divide-by-12 counter (MOD 12)
  • 7493 Four bit binary counter (MOD 16)
Read more :
1. Asynchronous Counter




















Some Synchronous Counter ICs
  • 74160 and 74162 Four bit decade counters (MOD 10)
  • 74161 and 74163 Four bit binary counters (MOD 16)

More reading ;
1. Binary Synchronous Counter
(4 bit Syn. Counter, Decade 4 bit Syn. Counter, Advantages of Synchronous Counters)











Design of Synchronous Counters
A summary of steps used in the design of this counter follows. In general, these steps can be applied to any sequential circuit. (sample1)(sample2(pdf))(sample3(pdf))

  1. Specify the counter sequence and draw the a state diagram.
  2. Derive a next-state table from the state diagram.
  3. Develop a transition table showing the flip-flop inputs required for each transition. The transition table is always the same for a given type of flip-flop.
  4. Transfer the J and K states from the transition table to Karnaugh maps. There is a K map for each input of each flip-flop.
  5. Group the K map cells to generate and derive the logic expression for each flip-flop input.
  6. Implement the expressions with combinational logic, and combine with the flip-flops to create the counter.



Some Up/Down Synchronous Counter ICs
  • 74190 Four bit up/down decade counter (MOD 10)
  • 74191 Four bit up/down binary counter (MOD 16)

Read :
1. Bidirectional Counter














Synchronous 3-bit Up/Down Counter
























Counter Application
24-hour digital clock.









To know about 74LS293. It's can be as 3 bit, 4 bit ripple counter or divide by 2 circuit. Here.
Datasheet LS293.


Count 000 - 999 using DECADE COUNTER 74LS93.

2 comments:

  1. Salam tuan,

    saya mahu bertanya berkenaan up/down counter.

    Jika JK ff diganti dengan T ff, J dan K dihubungkan pada nod yang sama betul x?

    - Dila

    ReplyDelete